a) Field of the Invention
The present invention relates to a method for manufacturing a field emission device, and more particularly to a method for manufacturing a field emission device which emits electrons by controlling a gate potential.
b) Description of the Related Art
A field emission device includes an emitter (field emission cathode) which emits electrons from its pointed end or tip by focused electric field. For example, a flat panel display includes a field emitter array (FEA) comprising an arrangement of a large number of emitters. Each emitter controls the brightness, etc. of a corresponding pixel of the display.
FIGS. 7A to 7E illustrate a method for manufacturing a conventional field emission device. Firstly, an SiO.sub.2 layer is formed on a silicon substrate by thermal oxidation, after which an SiO.sub.2 layer 52 is formed by a predetermined pattern on the silicon substrate 51 by photolithography, as illustrated in FIG. 7A.
Next, using the SiO.sub.2 layer 52 as a mask, the isotropic etching of the silicon substrate 51 is conducted to form a silicon substrate 51a having a projecting part located under the SiO.sub.2 layer 52, as illustrated in FIG. 7B. In this case, the etching is finished before the removal of the SiO.sub.2 layer 52.
Following the above, a surface of the silicon substrate 51a is oxidized by thermal oxidation so that an SiO2 layer 54 is formed on a surface of a silicon substrate 51c as illustrated in FIG. 7C. The silicon substrate 51c is used as an emitter. The emitter 51c has a pointed end or a tip.
Next, as illustrated in FIG. 7D, niobium (Nb) is obliquely deposited to form gate electrode layers 53b and 53a on the SiO2 layers 54 and 52, respectively.
Subsequently to the above, that part of the SiO.sub.2 layer 54 which covers the tip of the silicon substrate 51c is removed by etching. As a result, the tip of the silicon substrate (emitter) 51c, whose bottom part is covered by an SiO.sub.2 layer 54a, reveals as illustrated in FIG. 7E.
In the field emission device manufactured in the above-described manner, a leak current and a short circuit can easily occur for the following three reasons:
The first reason is that when the gate electrode layers 53a and 53b are deposited obliquely as illustrated in FIG. 7D, the gate electrode layer 53a tends to be deposited also on the sides and lower surface of the SiO.sub.2 layer 52.
When Nb 50 is impinged vertically on the substrate as illustrated in FIG. 8A, the Nb layer 53a is hardly deposited on the lower surface (back surface) of the SiO.sub.2 layer 52. In this case, however, a gate diameter R1 is undesirably large. The gate diameter R1 is the diameter of a circular hole (gate hole) in the Nb layer (gate electrode layer) 53b deposited on the SiO.sub.2 layer 54. If the gate diameter R1 is large, a high voltage has to be applied to the gate 53b so that the emitter 51c can emit electrons. In order to lower the voltage, Nb 50 is impinged at an angle .theta. with respect to a direction (normal line) perpendicular to the substrate, as illustrated in FIG. 8B. Under this condition, the gate diameter RI is small. However, not only the Nb layer (gate electrode layer) 53b is deposited on the SiO.sub.2 layer 54, but also the Nb layer 53a is deposited thick on the sides and lower surface (back surface) of the SiO.sub.2 layer 52. Furthermore, a thin Nb layer 53c is deposited near the border of the SiO.sub.2 layers 52 and 54, and the Nb layers 53a and 53b are mutually connected.
When the top part of the SiO.sub.2 layer 54 is removed by etching afterwards, the thick Nb layer 53a may adhere to the top parts of the gate 53b and emitter 51c, as illustrated in FIG. 9A. The Nb layer 53a, which is in contact with the gate 53b and the emitter 51c in areas 62, causes a short circuit. Moreover, the above-mentioned etching may result in the thin Nb layer 53c adhering to the top part or vicinity of the emitter 51c or gate 53b, as illustrated in FIG. 9B. Though the Nb layer 53c does not cause a short circuit between the emitter 51c and the gate 53b, it causes the flow of a leak current.
The second reason is that the thickness of the SiO.sub.2 layer 54a is uniform as seen from FIG. 7E. In other words, the interval between the tip of the emitter 51c and the gate 53b is equal to that between the bottom part of the emitter 51c and the gate 53b. When the interval between the emitter and the gate is short, an intense electric field is applied not only to the tip of the emitter but also to the bottom part of the emitter, under which condition the electric breakdown can easily occur.
The third reason is that the SiO.sub.2 layer 54a is a thin layer having a uniform thickness, and a capacitance between the emitter 51c and the gate 53b is large.